Multi-level flash memory devices of NAND architecture are in an initial phase of development. This implies that many specific parameters of operation such as the timing of certain phases of operation, biasing voltages and the like cannot be optimally defined in the design stage before gathering clear responses from the silicon.
Therefore, in the development phase of the design of a new memory device, it is necessary to carry out the control algorithms of operation of the memory device with a sufficiently ample possibility of varying the operating parameters. All the possible alternatives of configuration should be selectable in the device in a definitive or permanent manner and/or in a test mode (non-permanent) manner in order to facilitate recognition of the most efficient settings during the testing phase.
Such an ample variability often makes the execution of the control algorithms when verifying the functioning of the memory device rather complex with inevitable negative effects on the performances of the memory device. For example, it is frequently the case in which the intervals of execution of certain phases of operation are longer than what would be necessary for a correct operation of the memory circuits. This is due to the excessively long processing times of the configuration data, which causes a decrement in performances that are not imposed by technological limits.
The problem is particularly felt if another aspect of these devices is considered, which is the need of storing information on all possible configurations. For example, in order to ensure that the charge time of a mode at a certain biasing voltage is selectable among eight different possible values, it is necessary to store at least three bits of information for indicating which, among the possible configuration choices, is the currently selected one. Therefore, three configuration fuses and/or three storage latches are required, as will be illustrated later.
By applying the same reasoning to all the parameters that would be useful to be able to select among a certain number of possible different values in order to be able to trim with a sufficient degree of freedom all the configurable parameters for optimal performances of a device, the total number of configuration bits to be stored may reach the order of several hundred. All or a good portion of these configuration bits need to be accessible to (read) by the embedded microcontroller that executes the main phases of operation (control algorithms) of the memory devices.
The burden in terms of area occupation for storing such a large number of selectable configuration bits is considerable. In fact, apart from the silicon area strictly intended for forming the fuses and/or storage latches, a significantly even larger silicon area is required for forming all the necessary connections to/from these storage elements from/to the embedded microcontroller.
Simplified functional diagrams of a typical multi-level NAND flash memory device are depicted in FIGS. 1 and 2. FIG. 1 is relative to the managing of the memory operations by the embedded micro-controller (μP). FIG. 2 is relative to the execution by the microcontroller of a certain algorithm flow (e.g., for providing a regulated biasing or control voltage to a certain node of the memory circuitry) of a value determined by the state of relative configuration fuses of the device. These fuses are set during the final fuse-burning step of the testing phase at the end of the fabrication process.
Often, in order to facilitate verification and comparison of alternative configuration choices during the testing phase of the device being fabricated, a number of latches that are eventually bi-univocally associated to the same number of fuses is formed. Bit values corresponding to the ones of a selected configuration may be loaded by the external testing machine in the latches. The loaded bit value of a latch is eventually XORed with the bit content of the corresponding fuse through respective selection multiplexers controlled by the embedded microcontroller of the device upon executing one of the control algorithms.
In this way, at the expense of additional silicon area required for forming a same number of latches as the contemplated number of fuses and the relative selection multiplexer and XOR gate, a preferred performing configuration of the fuses may be assessed in a quicker and easier manner before proceeding to the conditioning (burning) of the selected fuses. The burning renders the configuration of the fabricated device permanent.